July 9, 2001 – Today 0-In Design Automation, Inc., the leader in white-box verification technology, announced immediate availability of its Verification IP (VIP) suite. This suite of products allows an RTL core provider to deliver 0-In checkers to its customers without any additional licensing from .0-In. The first commercially available core to ship with 0-In checkers is the Xtensa IV configurable processor from Tensilica, Inc.

Assertions Capture Assumptions of Core Designers
“To a core provider, there is nothing more important than thorough functional verification,” noted 0-In CEO, Dr. L. Curtis Widdoes. “Assertions play a key role in the verification process by capturing the designer’s assumptions about how the core should operate and how the core integrator should use the core in a system-on-chip (SOC) design. Assertions are a form of verification intellectual property (IP) that can accompany the core itself.”

0-In Checkers are Ideal for Assertion-Based Core Verification
Within the 0-In White-Box VIP Suite, assertions are captured by checkers from the CheckerWare library. These testbench-independent checkers watch for violations of design intent during simulation and provide structural coverage information to show how well the core’s RTL structures and interfaces have been exercised. Protocol monitors for core interfaces can be built easily by combining checkers for individual protocol rules.

0-In checkers work seamlessly with all 0-In products, including CheckerWare Wizard, 0-In Check and 0-In Search. During stand-alone core verification, 0-In Check and 0-In Search provide more thorough verification and decrease the time-to-market for the core provider.

0-In Checkers Accelerate and Ease Core Integration
“Since 0-In checkers are specified with comment-based directives within the RTL, they travel along with the core itself,” said Dr. Widdoes. “Therefore, the core integrator receives a core including checkers that continue to watch for assertion violations during SOC simulation. 0-In checkers ensure that the integrator does not disobey the interface protocol rules or use the core in a way that violates the core designer’s assumptions. The VIP suite allows a core provider to give this capability to core integrators without any separate 0-In licensing.”

“If a core provider’s customers run with 0-In checkers in simulation, the result is decreased support costs for the core provider,” added Dr. Widdoes. “If the integrator misuses the core, he or she sees an easily diagnosed checker violation message in SOC simulation. This eliminates the category of support calls to the core provider that are ultimately traced to incorrect core integration or usage.” Beyond simulation, the core integrator can also use 0-In Search to amplify the SOC tests and ensure that all blocks mating to the core interfaces are designed correctly.

0-In Directives Automatically Adapt to Different Core Configurations
Many commercially available cores have configuration options that allow the core integrator to customize the core features for specific applications. When 0-In Check interprets the directives in the RTL, it also infers checker hookup details from the RTL itself. Many common configuration options, such as bus width and memory size, can be handled with no changes to the directive. 0-In Check automatically adapts the checker for the specific configuration and includes the appropriate checker in stand-alone core or SOC simulations.

Tensilica and its Customers Benefit from 0-In Checkers
The recently announced Xtensa IV processor from Tensilica is the first core to be shipped with 0-In checkers. "The Xtensa processor is both configurable -- offering thousands of permutations of configuration options -- and extensible -- automating the addition of user-defined instructions and execution units." said Kaushik Sheth, Chief Engineer at Tensilica. “Our design and verification engineers have found the adaptive 0-In checkers very effective at accommodating the different configuration options. Tensilica has been using 0-In products to provide high-quality verification for the Xtensa cores for more than a year and has made 0-In checkers an central essential part of our verification methodology.”

All Xtensa IV core customers receive RTL fully instrumented with 0-In directives for the protocol rules on the Processor Interface (PIF). Since these directives are comments, they do not have any adverse side-effects during core integration and SOC verification. Coincident with the Xtensa IV shipment from Tensilica, 0-In provides an Integrator Kit that allows the core customer to run simulations with 0-In checkers without additional cost or licensing. “The use of 0-In checkers internal to Tensilica helps us to provide a robustly verified core,” added Sheth. "And by shipping 0-In directives for interface rules checking for the Xtensa PIF, our customers can more easily detect and fix any core integration problems, which can accelerate their schedules and reduce our support costs at the same time."

About 0-In
0-In Design Automation, Inc. (pronounced “zero-in”) is a privately held electronic design automation (EDA) company providing functional verification products that help verify multi-million gate ASIC and SOC designs. 0-In was founded in 1996 and is based in San Jose, CA, with sales offices in Boxborough, MA and Austin, TX plus distribution in Japan through Pacific Design Inc. Leading-edge companies that have adopted 0-In tools and methodologies include AMD, Avaz Networks, Fujitsu, HP, Hitachi, Hughes, Lucent, National Semiconductor, Nortel, Sun, Tensilica and others. More information on 0-In is available at http://www.0-In.com.

Contact:
Steven D. White
0-In Design Automation
408-487-3649
swhite@0-In.com